1. Field of the Invention
The present invention relates, generally, to an integrated CMOS circuit design and, more specifically, to an integrated CMOS circuit in a semiconductor substrate having at least a first silicon layer, a stressed Si.sub.1-x Ge.sub.x layer and a second silicon layer wherein both at least one p-channel MOS transistor and at least one n-channel MOS transistor are formed in the semiconductor substrate.
2. Description of the Prior Art
When structures are miniaturized by the principle of similar downscaling in MOS technology, the properties of MOS transistors and CMOS circuits are essentially preserved in the micrometer range. However, short-channel and punch-through effects occur in the case of MOS transistors having channel lengths of less than approximately 200 nm.
Although these effects can be compensated for, in part, by an increased doping of the substrate, such a high doping of the substrate leads, inter alia, to impairment of the charge carrier mobility in the channel. The impairment of the charge carrier mobility in the channel becomes particularly apparent in p-channel MOS transistors.
In CMOS circuit arrangements, particularly invertors, NAND and NOR gates, shift registers, memory, and logic and analogue circuits, use is made of both n-channel MOS transistors and p-channel MOS transistors which must have not only unit voltage equality in terms of magnitude but also the same transconductance and the same saturation current. It has been proposed (see, for example, K. Hoffman, VLSI-Entwurf Modelle und Schaltungen (VLSI Design Models and Circuits), 3.sup.rd edition 1996, pages 333 to 339) to achieve the same transconductance and the same saturation current in otherwise identically constructed n-channel MOS transistors and p-channel MOS transistors by giving the channel of the p-channel MOS transistor a width-to-length ratio which is twice as great as that of the channel of the n-channel MOS transistor. This is intended to compensate for the hole mobility in the p-channel MOS transistor being less than, by a factor of 2, the electron mobility in the n-channel MOS transistor. However, the area and the stray capacitance in the p-channel MOS transistor are increased as a result of this measure.
A. Sadek et al., Solid-State Electronics, Vol. 38, No. 9, (1995), pages 1731 to 1734 and K. Ismael, Lecture at the International School of materials science and technology, Erice, Italy, Jul. 13, to 24, 1995, pages 19 to 20 have proposed increasing the hole mobility in the channel of a p-channel MOS transistor by providing a layer of stressed Si.sub.1-x Ge.sub.x in the region of the channel. This layer is stressed by virtue of the fact that it has the lattice constant of monocrystalline silicon. The lattice in this layer is matched in the xy plane. For this reason, compressive stress exists in the x and y directions in the SiGe, while tensile stress is present in the z direction, which corresponds to the growth direction. One speaks of pseudomorphic layers in the context of heterostructures which are elastically stressed in this way. In order to produce a CMOS circuit, the p-channel MOS transistors are formed with a channel containing an Si.sub.1-x Ge.sub.x layer and the n-channel MOS transistors are formed with a channel made of monocrystalline silicon. Two separate process blocks are required here in order to produce the p-channel MOS transistors and the n-channel MOS transistors.